Instruction Set Architecture
ISA Levels
ISA is the abbreviation for Instruction Set Architecture. MIPS processors have been in production since 1988. Over time several enhancements of the architecture were made. The different revisions which have been introduced are MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V. Each revision is a superset of its predecessors. When MIPS was spun out of SGI again in 1998, they refocused on the embedded market. At that time, this superset property was found to be a problem, and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture. Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit and 64-bit MIPS processor, respectively.
MIPS I
This is the basic MIPS instruction set as implemented by the original R2000 and R3000 processors.
MIPS II
MIPS II was introduced by the R6000. It adds load linked, store conditional and branch likely instructions. The FPU's instruction set was improved by support of 64-bit loads and stores which halved the number of instructions needed to load or store a double precision floating point register when compared to MIPS I.
MIPS III
MIPS III was introduced 1992 in the R4000. It adds 64-bit registers and integer instructions and a square root FP instruction.
MIPS IV
MIPS IV adds conditional moves and an inverse square root FPU instruction. The R8000 was the first to implement the MIPS IV instruction set.
MIPS V
MIPS V was specified in 1994 by SGI but never actually implemented by any processor. MIPS64 is a superset of MIPS V
MIPS32
MIPS32 is the 32-bit subset of MIPS64. The current version is MIPS32 Release 5. Most MIPS32 cores shipping today implement Release 2 of the architecture.
MIPS64
MIPS64 is a superset of the MIPS V. The current version is MIPS64 Release 5. Most current production MIPS64 cores implement Release 1 of the MIPS64 architecture but a few also implement Release 2.
MIPS32/64 Release 2
Release 2 improves SMP support including the PAUSE instruction and more memory barriers (SYNC).
On the privileged architecture side it added support for JTLBs larger than 64 entries, large set associative FTLBs, scratch registers, and external interrupt controllers.
It also standardised system-level SMP components (CM, GIC, IOCU)
MIPS32/64 Release 3
Release 3 added the MicroMIPS instruction set and the MCU ASE. It also added TLB invalidate instructions and support for IEE-754-2008 FPU.
On the privileged architecture side it added read inhibit (RI) and execute inhibit (XI) bits to the TLB. It also added EVA to extend the usable virtual address space, and hardware page walking.
MIPS32/64 Release 5
Release 5 added the VZ module to support hardware assisted virtualisation, and the MSA SIMD module.
MIPS32/64 Release 6
Release added the following fonctionalities:
- a new family of branches with no delay slot:
- unconditional branches (BC) & branch-and-link (BALC) with a 26-bit offset,
- conditional branch on zer/non-zero with a 21-bit offset,
- full set of signed & unsigned conditional branches compare between two registers (eg. BGTUC) or a register against zero (eg. BGTZC),
- full set of branch-and-link which compare a register against zero (eg. BGTZALC).
- index jump instructions with no delay slot designed to support large absolute addresses.
- instructions to load 16-bit immediates at bit position 16, 32 or 48, allowing to easily generate large constants.
- PC-relative load instructions, as well as address generation with large (PC-relative) offsets.
- bit-reveral & byte-alignement instructions (previously only available with the DSP extension).
- multiply & divide instructions redefined so that they use a single register for their result).
- instructions generating truth values now generate all zeroes or all ones instead of just clearing/setting the 0-bit,
- instructions using a truth value now only interpret all-zeroes as false instead of just looking at the 0-bit.
Release 6 also removed infrequently used instructions:
- some conditional moves
- branch likely instructions (deprecated in previous releases).
- integer overflow trapping instructions with 16-bit immediate
- integer accumulator instructions (together HI/LO registers, moved to the DSP ASE)
- unaligned load instructions (LWL & LWR), (requiring that most ordinary loads & stores support misaligned access, possibly via trapping and with the addition of a new instruction (BALIGN))
Release 6 also reorganize the instruction encoding, freeing space for future expansions.
Application Specific Extensions (ASE)
DSP ASE
The DSP ASE is an optional extension to the MIPS32/MIPS64 release 2 instruction sets which can be used to accelerate a large range of "media" computations - particularly audio, since TV-resolution video is way beyond the power of general-purpose CPUs for the next few years. The DSP ASE assumes that you're running on a Release 2 chip since there are things that are in Release 2 that are critical to the performance of media applications written using the DSP ASE.
Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for its particular relevance to some key algorithm.
Its main novel features (vs original MIPS32):
- Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).
- Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").
- The existing MIPS32 instruction set includes integer multiplication and multiply-accumulate which delivers results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of multiply-accumulate.
- SIMD instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).
- SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.
To write DSP-ASE-enabled programs, you'll need to write assembler code or use the "intrinsics" (built-in pseudo-subroutines) which are more or less 1-to-1 with the underlying instructions.
Linux 2.6.12-rc5 starting 2005-05-31 adds support for the DSP ASE. Note that to actually make use of the DSP ASE a toolchain which support this is required. As of this writing only MIPS SDE has such support.
Books
The MIPS instruction set is by far too complex to be covered on this page. The freely available CPU specs are not an easy reading for a first time MIPS'er either. So here are some literature recommendations in no particular order:
