Linux/MIPS is a port of Linux to the MIPS architecture. It is available under the terms of the GNU General Public License.
|| linux-mips.org moved to new server
In the past few days linux-mips.org moved to a new server. All services except SMTP are now also available via IPv6. Thanks to Imre Kaloz for hosting linux-mips.org on openwrt.org for several years. Thanks also to Imgtec / PRPL for sponsoring the new machine!
|| CVE-2014-0160 on linux-mips.org
Until 2014-04-08 linux-mips.org was running an OpenSSL configuration vulnerable to the Heartbleed CVE-2014-0160 bug. The issue has been fixed and all affected SSL keys and certificates have been revoked and replaced.
The use of SSL encrypted services on linux-mips.org is optional; all services are also available via the traditional unencrypted HTTP protocol. As such only paranoid users, users of linux-mips.org's HTTP services and users that are using the same password on other sites are recommended to change their passwords.
Access to linux-mips.org's crown jewels such as the git source archives was not affected by the Heartbleed issue.
|| MIPS(r) P5600 Superscalar Multiprocessor Core Family
The MIPS P5600 processor IP core is the first member of the Warrior generation of MIPS CPU cores from Imagination Technologies. It delivers industry leading 32-bit performance with class-leading low power characteristics, and in a silicon footprint up to 30% smaller than comparable alternatives in the industry. The P5600 CPU core was designed for the performance and features required for tomorrow's mainstream connected consumer electronics including smartphones, tablets, connected TVs and set-top boxes. However, the rich and broad feature set extends applicability into a variety of networking applications, from residential gateways to network appliances and microservers.
|| Broadcom announce XLP9xx MIPS64r5 cores http://www.linleygroup.com/newsletters/newsletter_detail.php?num=5015
|| Cavium announce OcteonIII MIPS64r5 processors: http://www.cavium.com/newsevents_Cavium_OCTEON_III_Imagination_Technologies_MIPSr5_architecture.html
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