The R4600 Orion started shipping in 1994 as the first microprocessor developed by Quantum Effect Devices, Inc. in collaboration with Integrated Device Technology, Toshiba Corporation, and NKK Corporation. R4600 implements the MIPS III instruction set in a simple but effective 5-stage pipeline. It's very similar to the R4000 and R4400 processors but unlike these there is no integrated second level cache controller. R4600 has 16Kb Instruction and 16Kb Data L1 caches like R4400, but it is two-way set associative (as opposed to the R4400 which is direct mapped). Cache line size is fixed at 32 bytes.
R4700RM 200 C workstation. Linux supports the R4700 but this hasn't actually been tested since several years.
SGI Indy specifics
R4600 processor modules for the Silicon Graphics Indy were available in several versions:
- 100MHz without second level cache controller
- 100MHz with 512kB of second level cache controlled by an external controller
- 133MHz without second level cache controller
- 133MHz with 512kB of second level cache controlled by an external controller