From LinuxMIPS
Revision as of 14:31, 3 August 2012 by Ralf (talk | contribs) (Remove stale links, mention Philips -> NXP transition.)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

The Poseidon family of SOCs was originally developed by Philips then transfered over to NXP.


PR31100 is is a single-chip, low-cost, integrated embedded processor. PR31100 consists of a 40MHz R3000 3.3V static CMOS CPU with 4 K Instruction / 1 K Data cache memory, without MMU, multiple DMA channels and a high-performance and flexible Bus Interface Unit (BIU) and external I/O modules.


Poseidon v1.0

PR31500 is a 37MHz R3000 3.3V static CMOS CPU with R3000A TLB and 4K Instrution / 1K Data cache. PR31500 also contains multi-channel DMA controller, ROM, Flash, RAM, DRAM, SDRAM, SRAM, and PCMCIA controller and Dual-UART, SPI and High-speed serial interface controllers. Philips licensed a version of Toshiba's R3900 MIPS RISC processor core for the PR31500.

TwoChipPIC (for Personal Intelligent Communicator) chipset consists of the PR31500 microcontroller and the UCB1100 analog interface chip. The UCB1100 provides a 12-bit audio codec and a 14-bit modem codec, a touchscreen interface, and a 10-bit A/D converter for measuring battery voltages and other analog inputs.


Poseidon v1.5

The PR31700 is a 75MHz R3000 (PR3901 Processor Core) with MMU, 4K Instruction / 1K Data cache. PR31700 also contains multi-channel DMA controller, ROM, Flash, RAM, DRAM, SDRAM, SRAM, and PCMCIA controller. It is also identical to the Toshiba 3912 processor from the TX39XX family. It is pretty clear that Philips licensed or bought this core directly from Toshiba.

The datasheet can be found here: http://www.nxp.com/acrobat_download2/various/PR31700USER_GUIDE_2.pdf

The TwoChipPIC Plus chipset consists of Philips™ PR31700 and UCB1200 analog chip.