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Revision as of 14:01, 2 January 2005 by Ralf (talk | contribs) (ISA -> Instruction Set Architecture, other small cleanups)
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  • Toshiba 300MHz R5900 MIPS IV core, FPU, 16 KB 2-way set-associative I-CACHE and an 8 KB 2-way set-associative D-CACHE, along with a 16 KB data scratchpad RAM; set of 128-bit multimedia extensions
  • 128bit Emotion Engine: two 128-bit VLIW vector units: VU0, VU1; 10 DMA channels; MPEG decoder
  • 32 Mb PC800 Direct Rambus (Direct RDRAM) memory
  • Sony Graphics Synthesizer™ graphic processor at 150MHz, 4Mb of 1024bit eDRAM
  • USB

External links