PMC Yosemite

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Revision as of 08:14, 21 November 2004 by Ralf (talk | contribs) ('''Architecture Issues''')
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General information

The PMC-Sierra Yosemite reference board has the Rm9000x2 processor. The Yosemite board has the Titan SoC which supports Dual core Rm9000x2, Gigabit Ethernet, PCI and Hypertransport.

Detailed Description

  • PMC-Sierra Yosemite Board Configuration:
  • Dual core Rm9000x2 operating at 1.0 Ghz
  • Upto 1 GB of DDR memory
  • Three onboard Gigabit Ethernet Interfaces
  • Hypertransport interface that supports upto 500 MHz Link Frequency. Currently, this interface is compatible with the Alliance Sipacket/Natasha HT-PCIX bridge and the PLX HT-PCIX bridge
  • Two PCI busses and four PCI slots
  • Two external and two native UARTS (16550 compatible)
  • I2C

Architecture Issues

The Titan Revision 1.0 and 1.1 support the three state MEI protocol. As a result of which SMP Linux can only be supported with a hack to the Linux MM to disable page sharing. The newer revision of the chip (1.2) has this fixed and supports the five state MOESI protocol

The Titan 1.0 and 1.1 MAC subsystem does not support IP header alignment for incoming packets. As a result, the Linux driver has to do an extra copy for each incoming packet before passing the packet to the higher layers of the network stack. This is fixed in Titan 1.2.

Linux Support

Linux 2.4 supports all revisions of Titan but doesn't take advantage of Titan 1.2 an newer. Linux 2.6 removed most of the backward compatibility code for Titan revisions older than 1.2 but takes full advantages of features only available in this revison.