NEC VR4100

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Revision as of 04:21, 29 January 2006 by McNeight (talk | contribs) (V<sub>R</sub>4133: from NEC VR4133)
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The NEC VR4100 series of CPUs are based on the MIPS R4000 core.





The NEC VR4133 is a 200 Mhz processor with 16 KB of Primary Instruction cache and 16 KB of Primary Data cache. It has 32 TLB entries. The primary data cache line size is 32 bytes and the primary instruction cache line size is 32 bytes. Currently, this processor is fully supported in Linux versions 2.4 and 2.6.

See Also



The VR4181A (µPD30181A) is a 131 MHz 64-bit MIPS CPU that roughly implements the (MIPS III ISA, (without FPU, LL, and SC instructions) and MIPS16), plus interfaces for TFT/STN LCD display, dual CompactFlash, 3 UARTs, IrDA, I2C, 64 parallel I/O, RTC, watchdog timer, keyboard, USB, touch, audio I/O, and ISA-subset expansion bus.


Datasheets are available from NEC Electronics search page.

External links