Difference between revisions of "Memory consistency"
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== Consistency models on MIPS systems ==
== Consistency models on MIPS systems ==
The consistency model of a system is influenced by both the processor and the rest of the system. For this reason below
The consistency model of a system is influenced by both the processor and the rest of the system. For this reason below both the system and processor . Multiprocessor kernels also run on the MIPS 34K but this really is a singlemultithreadedcore which is presented to the kernel and applicationssoftware this looks like processor consistency.
Revision as of 14:31, 26 July 2007
This is a term which is used in the manuals of some of the older MIPS processors including the R4000 and R10000 but very rarely elsewhere. It has a quite reasonable definition in the R4000 User's Manual which also used to be available as an application notice. The catch - the manual doesn't make it explicit that the R4000 is strongly ordered. I (Ralf) believe this is because reordering may also happen at system level, so giving the promise just in the processors manual is worth much. The situation of the R10000 is similar sequentially ordered.
Sequential ordering was defined by Leslie Lamport as "...the results of any execution is the same as if the operations of all the processors were executed in some sequential order, and the operations of each individual processor appear in this sequence in the order specified by its program."
The system provides sequential consistency if every node of the system sees the (write) operations on the same memory part (page, virtual object, cell etc) in the same order, although the order may be different from the order as defined by real time (as observed by hypothetical external observer or global clock) of issuing the operations.
This is a slightly more relaxed consistency model than sequential ordering. It only guarantees that writes on one particular processor are being seen by another processor in program order. Processor consistency is also known as PRAM (pipelined random access memory) or FIFO consistency.
This model basically gives no guarantee. R->R, R->W, W->R and W->W reordering are allowed. To allow software to control reordering the SYNC instruction must be used.
The SYNC instruction
Introduced by the R4000 in 1991 this instruction is the safety net of the MIPS III and later architectures. The SYNC instruction contains a 5 bit field with vendor specific semantics. The standard SYNC instruction has these five bits zeroed; other values are reserved for implementation specific variants of SYNC.
The LL and SC instructions
LL, SC and their 64-bit brothers LLD and SCD are defined by the MIPS32 and MIPS64 architecture to not imply a SYNC instruction. Which doesn't forbid an implementation to do it anyway and indeed R4000 and R4400 processors (which predate MIPS32 and MIPS64 by many years) SC and SCD imply a SYNC instruction. The R10000 on the other hand doesn't.
Consistency models on MIPS systems
The consistency model of a system is influenced by both the processor and the rest of the system. For this reason the table below describes both the system and processor together. An "X" indicates that a particular ordering is relaxed. Multiprocessor kernels also run on the MIPS 34K but this really is a single, multithreaded, in-order core which is presented to the kernel and applications: to software this looks like processor consistency.
Consistency models on other architectures
- http://www.rdrop.com/users/paulmck/scalability/paper/ordering.2006.03.13a.pdf A good paper on memory consistency in the Linux kernel and many of the supported architectures.
- R4000 User's Manual, 2nd Edition
- R10000 User's Manual
- MIPS32 Architecture Reference Manual
- MIPS64 Architecture Reference Manual