Instruction Set Architecture
ISA is the abbreviation for Instruction Set Architecture. MIPS processors are being made since 1988. Over time several enhancements of the architecture were made. Of MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V each was a superset of it's predecessors. When MIPS was spun out of SGI again in 1998 and refocused on the embedded market this superset property was found to be a problem and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture. Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit rsp. 64-bit MIPS processor, however.
MIPS II was introduced by the R6000. It adds load linked, store conditional and branch likely instructions. The FPU's instruction set was improved by support of 64-bit loads and stores which half the number of instructions need to load or store a double precission floating point register on MIPS I.
MIPS III was introduced 1992 in the R4000. It adds 64-bit registers and integer instructions and a square root FP instruction.
MIPS IV adds conditional moves and an inverse square root FPU instruction. The R8000 was the first to implement the MIPS IV instruction set.
MIPS V was specified in 1994 by SGI but never actually implemented by any processor. MIPS64 is a superset of MIPS V
MIPS32 is the 32-bit subset of MIPS64.
A superset of the MIPS V and includes special multiply-accumulate, conditional move, prefetch, wait, and leading zero/one detect instructions.
MIPS32 V2.0 and MIPS64 V2.0
Application Specific Extensions (ASE)
The MIPS instruction set is by far to complex to be covered on this page. The freely available CPU specs are not an easy reading for a first time MIPS'er either so here a literature recommendations in no particular order.