# Instruction Set Architecture

## Contents

## ISA Levels

ISA is the abbreviation for *Instruction Set Architecture*. MIPS processors are being made since 1988. Over time several enhancements of the architecture were made. Of MIPS I, MIPS II, MIPS III, MIPS IV and MIPS V each was a superset of it's predecessors. When MIPS was spun out of SGI again in 1998 and refocused on the embedded market this superset property was found to be a problem and the architecture definition was changed to define a 32-bit MIPS32 and a 64-bit MIPS64 architecture. Frequently the terms MIPS32 and MIPS64 are meant to indicate some generic 32-bit rsp. 64-bit MIPS processor, however.

## MIPS I

This is the basic MIPS instruction set as implemented by the original R2000 and R3000 processors.

## MIPS II

MIPS II was introduced by the R6000. It adds load linked, store conditional and branch likely instructions. The FPU's instruction set was improved by support of 64-bit loads and stores which half the number of instructions need to load or store a double precision floating point register on MIPS I.

## MIPS III

MIPS III was introduced 1992 in the R4000. It adds 64-bit registers and integer instructions and a square root FP instruction.

## MIPS IV

MIPS IV adds conditional moves and an inverse square root FPU instruction. The R8000 was the first to implement the MIPS IV instruction set.

## MIPS V

MIPS V was specified in 1994 by SGI but never actually implemented by any processor. MIPS64 is a superset of MIPS V

## MIPS32

MIPS32 is the 32-bit subset of MIPS64.

## MIPS64

MIPS64 is a superset of the MIPS V.

## MIPS32 V2.0 and MIPS64 V2.0

## Application Specific Extensions (ASE)

### DSP ASE

The DSP ASE is an optional extension to the MIPS32/MIPS64 release 2 instruction sets which can be used to accelerate a large range of "media" computations - particularly audio, since TV-resolution video is way beyond the power of general-purpose CPUs for the next few years. The DSP ASE assumes that you're running on a Release 2 chip since there are things that are in Release 2 that are critical to the performance of media applications written using the DSP ASE.

Unlike the bulk of the MIPS architecture, it's a fairly irregular set of operations, many chosen for its particular relevance to some key algorithm.

It's main novel features (vs original MIPS32):

- Saturating arithmetic (when a calculation overflows, deliver the representable number closest to the non-overflowed answer).

- Fixed-point arithmetic on signed 32- and 16-bit fixed-point fractions with a range of -1 to +1 (these are widely called "Q31" and "Q15").

- The existing MIPS32 instruction set includes integer multiplication and multiply-accumulate which delivers results into a double-size accumulator (called "hi/lo" and 64 bits on MIPS32 CPUs). The DSP ASE adds three more accumulators, and some different flavours of multiply-accumulate.

- SIMD instructions operating on 4 x unsigned bytes or 2 x 16-bit values packed into a 32-bit register (the 64-bit variant of the DSP ASE supports larger vectors, too).

- SIMD operations are basic arithmetic, shifts and some multiply-accumulate type operations.

To write DSP-ASE-enabled programs, you'll need to write assembler code or use the "intrinsics" (built-in pseudo-subroutines) which are more or less 1-to-1 with the underlying instructions.

Linux 2.6.12-rc5 starting 2005-05-31 adds support for the DSP ASE. Note that to actually make use of the DSP ASE a toolchain which support this is required. As of this writing only MIPS SDE has such support.

## Books

The MIPS instruction set is by far to complex to be covered on this page. The freely available CPU specs are not an easy reading for a first time MIPS'er either so here a literature recommendations in no particular order.