Cpu features

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Linux/MIPS supports a wide range of processors that differ slightly in many features. Kernels that support many different processor types are possible but such a kernel will be relativly large and slow compared to one that supports the bare minimum. <asm/cpu-features.h> contains a number of macros that allow kernel code to be written in a way such that during compilation it will be optimized for a particular target platform.

cpu_has_tlb 
Set if a processor has a TLB. Linux/MIPS does currently not support TLB-less processors.
cpu_has_4kex 
cpu_has_4ktlb 
cpu_has_fpu 
True if the processor has a FPU.
cpu_has_32fpr 
True if the processor supports the 32/32  model, that is it has 32 double precission registers.
cpu_has_counter 
cpu_has_watch 
cpu_has_mips16 
True if the processor supports the MIPS16 extension.
cpu_has_divec 
True if the processor supports a Nevada-style separate exception vector for interrupts.
cpu_has_vce 
True if a processor has virtual coherency exceptions.
cpu_has_cache_cdex_p 
cpu_has_cache_cdex_s 
cpu_has_prefetch 
True if the processor supports a prefetch instruction and the prefetch instruction actually delivers some performance. The latter condition is not true for the R5000 for example which implements the prefetch instructions as nops. Conditional prefetches are a bad idea, so you really want to define this as a constant only.
cpu_has_mcheck 
True if the processor supports a machine check exception.
cpu_has_ejtag 
True if the system supports EJTAG.
cpu_has_llsc 
True if the system has load linked</code and <code>store conditional instructions.
cpu_has_vtag_icache 
True if the processor has a virtually tagged I-cache.
cpu_has_dc_aliases 
True if the D-cache of the processor might suffer from virtual aliases.
cpu_has_ic_fills_f_dc 
True if the I-cache may do refills on misses directly from the I-cache.

I-Cache snoops remote store. This only matters on SMP. Some multiprocessors such as the R10000 have I-Caches that snoop local stores; the embedded ones don't. For maintaining I-cache coherency this means we need to flush the D-cache all the way back to whever the I-cache does refills from, so the I-cache has a chance to see the new data at all. Then we have to flush the I-cache also. Note we may have been rescheduled and may no longer be running on the CPU that did the store so we can't optimize this into only doing the flush on the local CPU.

cpu_icache_snoops_remote_store 

RM7000 and RM9000 may throw bizarre exceptions if not the whole cacheline contains valid instructions. For these we ensure proper alignment of signal trampolines and pad them to the size of a full cache lines with nops. This is also used in structure definitions so can't be a test macro like the others.

PLAT_TRAMPOLINE_STUFF_LINE 
cpu_has_nofpuex 
True if the CPU does not support FPU exceptions. This is needed for processors with R2000-style FPU coupling.
cpu_has_64bits 
cpu_has_64bit_zero_reg 
cpu_has_64bit_gp_regs 
cpu_has_64bit_addresses 
cpu_has_subset_pcaches 
cpu_dcache_line_size 
cpu_icache_line_size 
cpu_scache_line_size