Caches

From LinuxMIPS
Revision as of 13:08, 8 November 2004 by Ralf (talk | contribs)
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to: navigation, search

Cache Policies

MIPS processors implement several different cache policies. Virtually indexed or tagged caches tend to please hardware implementors, physically indexed caches are favoured by software people.

Physically indexed, physically tagged

This policy is implemented by the R2000 and R3000 processors. It avoids aliases by it's very nature, so doesn't need any cache flushes. It's therefore the prefered cache policy of software implementors.

Physically indexed, virtually tagged

This cache policy is implemented by the R6000. It's believed to be the only processor which ever implemented it. Some literature calls this policy outright useless but nevertheless something must have appealed the R6000 designers enough to go for it. Just to makes things even a little more interesting the R6000 cache and TLB implementations are closely related again in a unique way.

Virtually indexed, physically tagged

Probably the most wide-spread cache policy in modern MIPS processors. While being the favorite of hardware implementors it requires very careful software managment of caches. A few processors have such caches but also a sufficient degree of cache associativity to make them look to software like they're actually physically indexed, physically tagged, thus also inherting their software properties. The R10000 family has a unique solution in that it resolves aliases in hardware, invisible to the programmer. So while the hardware actually suffers from alias this never becomes software visible and caches effectivly behave like physically indexed, physically tagged caches.

Virtually indexed, virtually tagged

A policy that maximises the pains of cache managment if applied to writeback caches. In the MIPS world it therefore only has been used for the instruction caches of the R8000 and the SB1 and 20kc cores and only with an additional address space identifier as a tag. The net result pleases hardware implementors because instruction cache lookup can start before completion of the address translation in the TLB. It also inflicts little pain on the OS implementation.

Terminology

Caches suffering from aliases are sometimes known as non-coherent. This terminology isn't used in the MIPS world however as for cache managment software there still is a relation.

Cache aliases are also known as synonyms in the literature but the MIPS world prefers the term aliases.

Common Abreviations

I-cache 
instruction cache.
D-cache 
data cache.
S-cache 
secondary cache.
PIPT 
physically indexed, physically tagged.
PIVT 
physically indexed, virtually tagged.
VIPT 
virtually indexed, physically tagged.
VIVT 
virtually indexed, virtually tagged.

External Links

  • ISBN 0-2016-3338-8 432 UNIX(R) Systems for Modern Architectures