Transparent Huge Pages

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Transparent Huge Page support for MIPS is currently under development. THP is currently planned to only be available for 64-bit kernels. A git tree contains the development code.

Hardware requirements

Only R4000-style TLBs are supported. R8000 support may be added in the distant future. The NEC VR41xx processors have such a TLB but do not support the necessary huge page size not even for 4kB base page size so huge page support is not possible for them.

Size of Huge Pages

Due to the page table layout doubling the base page size means the huge page size will increase by a factor of 4. These are the numbers:

Base Page Size Huge Page Size Size of pgd Size of pmd and pte Address space Comments
4kB 2MB 8kB 4kB 40
8kB 8MB 8kB 8kB 43 R8000 and Cavium cnMIPS cores only
16kB 32MB 16kB 16kB 46
32kB 128MB 32kB 32kB 49 Cavium cnMIPS cores only
64kB 512MB 64kB 64kB 52

Only the very largest systems will gain from enabling huge page support with a very large base page size.

Page Table Structure

Similar to what x86 does MIPS also folds the 2MB ptes into the PMD thus eleminating the last level of the page table.

Standard 4K pages on a 64-bit kernel, each PTE entry corresponds to a single EntryLo0 or EntryLo1 value, the standard pages have a size specified by PageMask
2M Huge Pages on a 64-bit kernel, each PAGE_HUGE PMD entry corresponds to an (EntryLo0,EntryLo1) pair, so the PAGE_HUGE page has a size twice that indicated by PageMask

Each diagram illustrates the case of a particular page size. In an actual page table both sizes will coexist. The TLB reload code and memory management code can distinguish between the normal and huge page case by testing the PAGE_HUGE bit.

See also