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The R5000 is a low-cost, dual-issue microprocessor with builtin FPU. Originally targeting the market of the R4600 the market of the R5000 were low-cost RISC workstations and high-end embedded applications such as routers. Its 5-stage pipeline is architecturally similar to the R4600 but with 32kB instruction cache and 32kB data cache its primary caches are twice as large. Another improvement over the R4600 is the integrated second level cache controller which reduces the access time over primary caches attached by an external second cache controller as it was done for a few R4600 systems such as the Silicon Graphics Indy. R5000 caches are not coherent.


Targeting different cost ranges in embedded applications many variations of the original R5000 architecture were developed. Some reduce the SysAD bus to just 32-bit for cost reasons, others halve the cache sizes or eleminate the second level cache controller. Popular variants were the RM5230, RM5321, RM5260, RM5261 and RM5270 and RM5271, sometimes also known under the codename Nevada.

Model I/D cache size SysAD bus width L2 cache interface CPU Clockspeed Package
RM5230 16/16 32 No 175MHz 128 PQuad
RM5260 16/16 64 No 200MHz 208 PQuad
RM5270 16/16 64 Yes 200MHz 304 SBGA
RM5231 32/32 32 No 250MHz 128 PQuad
RM5261 32/32 64 No 266MHz 208 PQuad
RM5271 32/32 64 Yes 266MHz 304 SBGA

SGI Indy specifics

R5000 processor modules for the Silicon Graphics Indy were available in several versions:

  • 150MHz without second level cache controller
  • 150MHz with 512kB of second level cache controlled by an external controller
  • 180MHz with 512kB of second level cache controlled by an external controller

The external cache controller used is the same as for Indy R4600SC processor modules. That also means the internal second level cache controller of the R5000 is not used although would be faster. Presumably that was done because it simplified the design. The second level cache does not therefore require special software support which Linux implements in sc-ip22.c.