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MIPS Magnum 4000 parts

To: riscy@pyramid.com
Subject: MIPS Magnum 4000 parts
From: adyer@zarniwoop.chi.il.us (Andrew Dyer)
Date: Thu, 12 Aug 93 07:23 PDT
Cc: riscy@pyramid.com
In-reply-to: Rogier Wolff's message of Thu, 12 Aug 93 08:21:31 +0200 <9308120621.AA20348@zen.et.tudelft.nl>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
   Date: Thu, 12 Aug 93 08:21:31 +0200
   From: wolff@zen.et.tudelft.nl (Rogier Wolff)
   Sender: owner-riscy@pyramid.com
   Reply-To: riscy@pyramid.com

   > The trick is that EISA and ISA are completely different, however through
   > an engineering trick they managed to put the two conectors in the same 
   > in such a way that there wouldn't be a motherboard realestate penalty for
   > having both busses.

   On second though, I can't substantiate the "completely different" part.
   I just don't know. However the fact that someone has an EISA system, which
   will take ISA cards doesn't mean that the ARCset supports the ISA part on
   the EISA connectors. 

EISA basically adds another 16 data bits to the 16 on the ISA bus
using a mechanical trick with the connector.  They also add some
specific EISA control signals.  The main "good thing" about EISA is
that all of the bus signals are sampled relative to a clock (no async
bus bullshit!).

The main trick is that since the ISA bus is asynchronous, all they had
to do was send out the correct signals at the correct clock periods,
and most ISA cards should work.  EISA supports ISA xfers to or from
other ISA boards, EISA boards, and/or platform resources.  EISA has
slot specific I/O addressing for EISA cards, and can arbitrate for the
bus using something other than the DMA controller :-o (although that
is supported).  EISA supports fast 8/16/32 bit cycles to memory, and
fast 8/16 bit cycles to I/O.  EISA has burst xfer modes.

--------------------------------------Ich mo"chte ein Eisba"r sein!
(1) adyer@zarniwoop.chi.il.us
(2) adyer@usr.com

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