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Re: R4000 chipsets

To: riscy@pyramid.com
Subject: Re: R4000 chipsets
From: Bill Broadley <broadley@neurocog.lrdc.pitt.edu>
Date: Thu, 12 Aug 1993 05:38:45 -0500 (EDT)
In-reply-to: <9308120900.AA01420@resi.waldorf-gmbh.de> from "Andreas Busse" at Aug 12, 93 11:00:43 am
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com

> It provides a complete interface to second-level cache, main memory, 
> and I/O for an R4000PC or R4400PC processor.

Sounds very good, getting the cheap cpu AND a 2nd level cache.

> IDT has announced plans to market this implementation in 3Q93.
> MIPS itself is developing a similar bridge that it expects Toshiba
> and NEC to begin selling in 3Q93.

Two bridge chips sets due out nowish good.

> The PICA bus provides 200 MBytes per second of peak bandwith (burst mode)
> to the memory and video subsystems. Three chips implement the interface
> to main memory; the memory controller (MC) and two data buffers. The MC
> provides address and control for up to 256 MB of DRAM.

PICA?? Is this proprietary? How wide?  Clock speed?

256 MB sounds good, I'm this means 32 bit wide simms which is good.

> That looks fine, at least for me.
> Has someone a phone number of Acer ?

    Acer Technologies Corp..... Tech Support .......... 408-922-0333

This sounds the best of all the choices, lets hope it's

I see no limitation that would keep this system from being a 
formidable, well balanced, 486 killer system.

Bill                                    1st>    Broadley@neurocog.lrdc.pitt.edu
Broadley@schneider3.lrdc.pitt.edu <2nd  3rd>                 Broadley+@pitt.edu
Linux is great.         Bike to live, live to bike.                      PGP-ok


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