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Re: Second level cache?

To: Tommy.Thorn@daimi.aau.dk
Subject: Re: Second level cache?
From: Andreas Busse <andy@resi.waldorf-gmbh.de>
Date: Wed, 11 Aug 93 12:19:45 +0200
Cc: riscy@pyramid.com
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
> I suppose the discussion came becourse there is evidence that cache
> size can influence performens (big news ;^) It is then a natural
> question to ask "Can we have more? How much will it cost?" That the
> ARCset didn't support it was/is non-obvious for the most of us. (Given
> that most of us don't have any info on the ARCset besides what's
> revealed in this forum.)

Yes, of course. I always go this way myself :-) Without asking for
more you'll never get more. 

>  > If you all insist on a 2nd level cache design, we should forget
>  > about the ARCset. That means in turn that we should forget about
>  > having a design within the next 12 months. I'm not sure what then
>  > happens to the group...

> Given this, we proberly don't wan't 2nd level cache, but don't flame
> us for having the discussion.

Sorry, it wasn't meant as flame. I just wanted to stop a discussion
which is substantial in general, but isn't very useful for this
particular design.
I have posted the pin description of the NEC address path controller
so that everybody in the list gets at least the idea of what this
chip does.
If you like, I can also post the pin descr. of the data path
controller. Perhaps things are clearer then.

You all might have noticed that the NEC chip has built-in EISA
support. That does not mean that we have to use EISA as our bus
system. The chip also provides a nearly complete 386 bus, so it
shouldn't be a problem to add some ISA chips.


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