Neil Russell writes:
> What I understand is that the ARC chipset supports a secondary cache
> similar to the way it does for the 486. It is not necessary to use
> the cache support signals from the R4k to have a secondary cache, although
> it may mean that this cache will take two cycles to access data where
> the R4000SC cache would take one. This may not be great, but it is still
> better than the cycles required to get data from DRAM.
Andreas Busse writes:
> 5. The R4200 ***DOES NOT*** support 2nd level cache. The Blockdiagram
> of ARCset shows no 2nd level cache, and there's ***NO SUPPORT*** at all.
> Finally, I simply don't understand why this discussion came up.
> I thought our goal was to design and produce a board with very good
> price/performance relation. Although the price of the ARCset isn't
> clear at the moment (which is not my or our fault, but NEC's) it seems
> that this is what we are looking for. It offers more speed than
> a R3081 solution probably for only few $s more.
I suppose the discussion came becourse there is evidence that cache
size can influence performens (big news ;^) It is then a natural
question to ask "Can we have more? How much will it cost?" That the
ARCset didn't support it was/is non-obvious for the most of us. (Given
that most of us don't have any info on the ARCset besides what's
revealed in this forum.)
> If you all insist on a 2nd level cache design, we should forget
> about the ARCset. That means in turn that we should forget about
> having a design within the next 12 months. I'm not sure what then
> happens to the group...
Given this, we proberly don't wan't 2nd level cache, but don't flame
us for having the discussion.