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Re: Mips chips/performance

To: riscy@pyramid.com
Subject: Re: Mips chips/performance
From: ronald%csunix.urc.kun.nl@kunrc1.urc.kun.nl (Ronald Schalk)
Date: Wed, 11 Aug 1993 11:45:43 +0200 (CET)
In-reply-to: <9308110735.AA22202@resi.waldorf-gmbh.de> from "Andreas Busse" at Aug 11, 93 09:35:20 am
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
> 1. The specs for the R4200 are probably *estimates*. I'm sure they are
>    a bit too high, but not much. The speed of the R4200 must be in
>    between a R3000/40 and a R4000PC/50, simply because
>    - it has 10 MHz clock less than the R4000PC/50 and
>    - it has 64bit wide bus and logic, which makes it faster than a R3000/40.

I guess by now we can close this discussion by voting for R4200.
Why:   1 This project started with the R3K andthe R4.2K is much faster,
         and this HAS FP-support. (No more discussion like 3051<->3081)

       2 It would make software easier, no FP-emulation needed :-)

       3 There are more important issues that have been put to the background
         e.g. ethernet,scsi,video,serial I/O, parallel ports, sound (?)

> 2. The FP92 specs of the R4200 are so good because most floating point
>    instructions have the same execution time as a real R4000 FPU has,
>    only MUL and DIV are slower.

Yes, especially considering that the R3051 was first seriously considered.

> 4. The R4200 has a larger primary cache (16k I + 8k D) than the R4000
>    (8k I + 8k D). I mentioned already that the MIPS R4000 machine I
>    am working on is sometimes 3 (!!) times slower than the R3000 machine
>    with 32+32k cache we have here too.
>    Although I don't believe that those 8k more speeds up the R4200
>    by nearly factor 2 (in comparison to the R4000PC), I'm sure that
>    the larger I cache results in a noticeable sustained speed up.

YES, I guess that's important too.

> 5. The R4200 ***DOES NOT*** support 2nd level cache. The Blockdiagram
>    of ARCset shows no 2nd level cache, and there's ***NO SUPPORT*** at all.
> The latter point should be one reason more to stop that 2nd level cache
> discussion. If we are going to use the ARCset, we won't have 2nd level
> cache. This is a fact unless someone finds an application around the R4200
> or Orion *with* 2nd level cache support.

Yes, it's important to drwaw the line somewhere, there's always something
bigger, better, faster, etc. But the main point is that the board has to
be affordabable. I guess the R4.2K gives us a viable alternative to the R3K.

Well closing off: 

Can we perform some kind of vote on the processor? Even though the 
pricing is not quite clear yet. I guess we can start talking again about 
the above mentioned issues??

Greetings Ronald

 * ing. Ronald Schalk                                               *
 * sectie COOS                                                      *
 * Universitair Centrum Informatievoorziening (UCI)                 *
 * Katholieke Universiteit Nijmegen (KUN)                           *
 * e-mail : R.Schalk@uci.kun.nl   snailmail: Geert Grooteplein 41   *
 * tel.   : +31 80 617997                    6525 GA Nijmegen       *
 * fax   :  +31 80 617979                    Nederland              *

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