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Re: R4xxx Cache size, pedantic ramblings

To: riscy@pyramid.com
Subject: Re: R4xxx Cache size, pedantic ramblings
From: Drew Eckhardt <drew@romeo.cs.Colorado.EDU>
Date: Tue, 10 Aug 1993 03:51:24 -0600
In-reply-to: Your message of "Tue, 10 Aug 1993 11:08:48 +0200." <9308100908.AA09361@liberator.et.tudelft.nl>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com

    Compare to R4000:
        6.  All instructions are 32 bits.
    This has nothing to do with caches.

Indirectly, it does.

I should have been more specific here : specifically, I was 
getting at the lack of variable sized instructions forcing the 
instructions to be bigger (ie, 32 bits for the R4000 vs. 8,16, etc. 
for the i486) meaning the R4000 will have larger code and will 
therefore require a larger cache to maintain the same hit-rate.

I should have generalized more and said 

"RISC chips have bigger code than CISC chips, and therefore will
need larger caches to have the same hit rate"



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