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Re: Second level cache?

To: riscy@pyramid.com
Subject: Re: Second level cache?
From: weingart@inf.ethz.ch
Date: Tue, 10 Aug 93 09:29:38 +0200
In-reply-to: Your message of "Mon, 09 Aug 93 22:08:21 MDT." <199308100408.AA14595@romeo.cs.Colorado.EDU>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
You write: 
Sie schreiben: 

> It could be configurable (ie, my i386 uses jumpers), the question is 
> can a second level cache be done within the constraints of our
> cost design goal.

What is our cost design goal?  $2000 US?  Less?  More?

> R4x00 SC and MC chips include support for a second level cache, ie you 
> throw enough SRAM on for tag, tag ECC, data, and data ECC with a 
> few PALs for address decode and have it.  However, preliminary reports 
> indicate the 4000SC has a ~$600 price tag rather than ~$300 for the 
> 4000PC, meaning using an SC is not practical in our design entirely
> because of the cost constraint.

For low cost, I would not think about the SC/MC chips.  They have
400+ pins, and that will be a nightmare to make a cheap board out of.

I was more thinking along the lines of a 4000PC, with an external
cache controller.  I don't know if it's possible, but that would
take our pin count down to ~180 pins...

|Tobias Weingartner  |    PGP2.x Public Key available at     |
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