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R4xxx Cache size.

To: riscy@pyramid.com
Subject: R4xxx Cache size.
From: wolff@erasmus.et.tudelft.nl (Rogier Wolff)
Date: Tue, 10 Aug 93 09:00:03 +0200
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
>    The R4xxxx has a larger internal cache.
>R4000 : 8K I, 8K D
>R4400 : 16K I, 16K D
>The maximum imposed by the R4000 architecture is 32K each for the primary
>cache.  I don't know about the 4200 since I don't have a data book in front
>of me like I do for the NEC Vr4000 and Vr4400, PC, SC, and MC variants :-)
Huh? Does that mean that the ARCHITECTURE defines a maximum CACHE size?
According to current definitions here at the computer architecture group,
cache size is an implementation aspect, and shouldn't be visible at the
architectural level.

This means that the R4xxx has a bad design: the design mixes implementation 
with architectural features. The R4000 isn't as clean as we thought. This
means that we can't use the R4000 as the processor.... :-)



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