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Re: Second level cache?

To: riscy@pyramid.com
Subject: Re: Second level cache?
From: Drew Eckhardt <drew@romeo.cs.Colorado.EDU>
Date: Mon, 09 Aug 1993 22:08:21 -0600
In-reply-to: Your message of "Mon, 09 Aug 1993 17:23:56 +0200." <9308091523.AA13831@neptune>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
    I don't know much about hardware design, but could you design the thing
    in such a way that you can plug in cache, when you need it.  IE: if you
    don't have the money, the board will run without the SC, and if you do,
    you just buy some SRAM, and plug 'er in...
    Or will this cause the logic to go beserk?

It could be configurable (ie, my i386 uses jumpers), the question is 
can a second level cache be done within the constraints of our
cost design goal.

R4x00 SC and MC chips include support for a second level cache, ie you 
throw enough SRAM on for tag, tag ECC, data, and data ECC with a 
few PALs for address decode and have it.  However, preliminary reports 
indicate the 4000SC has a ~$600 price tag rather than ~$300 for the 
4000PC, meaning using an SC is not practical in our design entirely
because of the cost constraint.

The question becomes : can we meet our cost target by having 
a second level cache *external* to the processor, with low
cost boards shipped with 0K SRAM.



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