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Re: Second level cache?

To: riscy@pyramid.com
Subject: Re: Second level cache?
From: Drew Eckhardt <drew@romeo.cs.Colorado.EDU>
Date: Mon, 09 Aug 1993 21:56:57 -0600
In-reply-to: Your message of "Mon, 09 Aug 1993 09:13:39 MDT." <9308091513.AA10979@agua.colorado.edu>
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
      > Adding the decreased locality of Unix+X11 over dos, the higher (100 Mhz
      > internal) clock rate, and mips binaries being bigger then 486 it would
      > seem that a large secondary cache would be necessary.  Based on a 486's
      > secondary cache being useful.
    The subject isn't that simple. For example the usefulness of the cache 
    greately depends on how the memory is interleaved 

Yes.  2-way interleaving can cut the wait states in half in the 
average case with a cache-miss, 4-way in half again, etc.  However,
the 4000, 4200, and 4400 are all 64 bit chips meaning you need 
a 128 bit wide memory subsystem for 2-way, 256 for 4-way.
    Also there is an issue of the internal cache size. An
    internal cache on a 486 is 16k 

No.  The internal cache on an Intel 486 is 8K combined I&D, although
IBM is building it's own 486's that may have a larger internal cache.

    but writethrough not write back. 

Yes.  This is very significant.  Also important are cache interleave,
line size, etc.  

    The R4xxxx has a larger internal cache.

R4000 : 8K I, 8K D
R4400 : 16K I, 16K D

The maximum imposed by the R4000 architecture is 32K each for the primary
cache.  I don't know about the 4200 since I don't have a data book in front
of me like I do for the NEC Vr4000 and Vr4400, PC, SC, and MC variants :-)
      > Any suggestions on how to get some numbers experimentally?
    Yea build an R4000 system with the desired level of interleaving; one with
    and one without secondary cache. Then run both systems :)



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