My personal opinion is Go, and that means R3081.
The 4200, which is both cheaper and faster than the 3081
is also shipping, albeit NEC is only making 10K 4000PC's and
4200's in a month.
It strikes me that if you are saturating a bus with
i/o, it doesn't matter if the CPU is doing it or if
it's DMA, you are bus limited. So I suggest considering
non-dma IDE and floppy interfaces.
You aren't saturating the bus.
You really want a DMA floppy interface (ie, wire the floppy
controller up as a slave device as it was intended to be) because
without it you have to sit in a loop while you read the track
(ie, 160ms) and can't be doing other things.
DMA transfers will move the same amount of data, but you can
do other things while the actual transfer (9K over 1/6th of a second
for a 1:1 interleaved 1.44M floppy) happens.
The IDE drives do have a sector buffer so it's not as critical,
but you could still gain something since IDE drives use a 16 bit
bus that (if standard) runs 8Mhz, 1 wait.
The existing IDE
driver uses cpu controlled transfers, which are to
a sector buffer that can be accessed at full speed.
Full ISA bus speed.
R3081 CPU $80.00
Wrong. All of the quotes we have on the R3081 in quantities
we can use are at least $300, NEC press releases have said $70
for the 4200 but no one has talked to a real distributor who sets
prices for small quantities.
Low quotes on the R3051 (ie, no floating point) were in the
FYI, I talked to NEC today and they refered me to the local
distributor for their parts
Compass Marketing +1 (303) 721-9663
I didn't get a chance to call during business hours and there's nothing
to say the distributor will be able to give us prices / parts given the
low (10K/month) production rate at this point, but I finally have a number
and can try tomorrow.
MOM memory/video/keyboard i/f $30.00
The MOM really doesn't do what we want - no variable bus sizing for the
peripherials, no slave mode DMA for the SCSI / ethernet, the bus master
has to have 3051 / 3081 / 3041 compatable signals (ie Mux'd address/data),
etc. In other words : the simplest way to do it hardware is with something
other than the MOM (ie, arc), the external hardware needed on the MOM makes
The simplest MOM solution (hardware) may be to use a 3041 running real
time software in the sample design in place of the ILAC ethernet busmaster
device, which in turn acts as a slave mode DMA controller, etc. but software
would be tricky.
smc37c652 floppy/serial/ide/parallel $20.00
dual-port ram ethernet (8390) _or_ bus-master ethernet (79900) $20.00
Do you have actual quotes on this, or is it an estimate? If it's the
former, does it include the price of the memory, arbiter PAL (or some
fraction of some other PAL we use) for the shared memory, tranciever,
etc (ie, everything in the NS app. note).
bus-master SCSI (53cf90) _or_ how big is the fifo on these? $25.00
The 53cf90 is *not* a busmaster, it's a slave dma/pio device with a 16 byte
FIFO. However, as I have stated in the past, with a *sane* architecture
(ie, the m68k which runs all DMA through the MMU) you get scatter gather
for slave mode devices and you don't need to bus-master. For the
typical SCSI command using this chip we'll service *at most* four
interrupts where we can transmit data immediately without sitting in a busy
loop of any sort.
They (IDT) say 35 MIPS, 11 MFlops. I believe that's on the
order of a 486dx2-66.
Sytem performance would be (because of the local bus peripherals) on the
same order. Correct me if I'm wrong.
It really depends -
The interleaved VRAM (ie, 64 bit access) will allow far more video
bandwidth than with the DRAM used on cheap localbus video boards (where
you loose 45-90M/sec to the serializers if you can run at that resolution)
and the 40Mhz R3000 will do graphics primitaves faster than an S3.
While the 486 looks OK under some benchmarks (SpecFP), real
world and other benchmarks are more favorable towards the R2000/R3000
FPU's even at a much lower clock speeds (not the 40/66 to 100/66 ratios
we'd have with the various proposed solutions).
In the 486's favor is the second level cache, which may have a significant
effect on it's relative performance in real world software.
The various MIPS chips have at least double the internal cache,
separate I & D so locality is maintained better, but you're going
to loose something without having a second level cache like
the 486 boards have. How much cache is the important issue here,
since there are diminishing returns and the hit rate depends on the
design (set associative vs. direct mapped). Some one needs to
*research* the issue.
IMHO : there are probably more chips out there than the
IDT3081/MOM combination, ie the 4200 or 4000PC and NEC ARC chipset,
that should be considered before a design of any kind happens.
Also, there are design issues that *need* resolving which will have
a very significant effect on the final cost, market size,
and performance of the system.
IMHO the decision to provide an expansion path beyond the local bus
connector for Waldorf's board, memory, and pin-compatable chips,
second level cache, and use of the NEC manufacturing kit rather than
our own design built arround the ARC chipset are the most significant
of these issues.