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Re: Mips Chips from NEC

To: riscy@pyramid.com
Subject: Re: Mips Chips from NEC
From: Andreas Busse <andy@resi.waldorf-gmbh.de>
Date: Thu, 29 Jul 93 16:51:03 +0200
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
> Any reason the R4200 is being compared to the SC chips and not the PC?
> Based on pin count alone I'd expect the PC at 179 pins to be a fair 
> amount cheaper then the SC at 447 pins.  Or is the 4200 a SC??

I don't know. So far I know is the R4200 a PC version.
It's *very* difficult to get informations about the R4200.
An engineer at NEC asked "no problem, how many do you want to buy ?"
while a distributor told me that he had never heard about that part
and that NEC doesn't produce it !
Seems we are a bit ahead of the technology...

However, I've got a data sheet for the NEC VRX / uPD30450. It looks
like that this is what we call the R4200. At least the detail that
this CPU has a 5-stage pipeline instead of the 8-stage pipeline used
in the R4000 and R4400 makes it very probably that it is the R4200.

Some Specs quoted from the sheet (Feb. 93):

Input Clock:            40 MHz
Operating Clock:        80 MHz
I-Cache:                16 kB
D-Cache:                 8 kB
Power Consumption:       2 W

System interface compatibel with the Vr4000 series.
Instruction set compatibel with the Vr4000 series.

So far, so good. But there's one important thing, probably a great
disadvantage for some of the group: The VRX has ***NO*** FPU !!!

Again, qouted from the data sheet:

All floating point instructions, as defined in the MIPS ISA for
the floating-point coprocessor CP1, are processed by the same
hardware as for the integer instructions. That is to say, there
is no separate floating point coprocessor. However, the execution
of floating point instructions can still be disabled via the
coprocessor usability CU bit defined in the CP0 status register.
[end of qouted material]

Here are some examples of floating point instruction timings:
(in pipeline clock cycles)

Insn            S       D
Add.fmt         3       3
Sub.fmt         3       3
Mul.fmt         11      20
Div.fmt         28      57
Sqrt.fmt        28      57
Abs.fmt         1       1
S=single prec., D=double prec.

So far I understand the data sheet, these instructions
are executed in parallel to loads, stores and so on.
The CPU stalls when, for example, an int-multiply is
in progress and a second multiply, no matter what format,
is to be executed.
I would say, except of Mul and Div, this is the same
timing as the R4000 and R4400 have. I can't decide
if the performance of Mul and Div satisfies the requirements
of the group. All I can say is: It's ok for *me*.

Any comments ? Please - if we really want to make hardware
instead of vapor-ware, wakeup, guys. Here's something to discuss.


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