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arc 100 150 manufacturing kits

To: riscy@pyramid.com (Mips 3000)
Subject: arc 100 150 manufacturing kits
From: Bill Broadley <broadley@neurocog.lrdc.pitt.edu>
Date: Tue, 27 Jul 1993 04:00:53 -0500 (EDT)
Reply-to: riscy@pyramid.com
Sender: owner-riscy@pyramid.com
I got some info on the arc 100 and 150 kits.

They seem to be centered around the MCT-ADR address path controller and a
MCT-DP data path controller.

MCT-ADR: (PD31432) 240 pin PQFP package 1.8 watts
        Interfaces to the Vr4000 microprocessors
        8 to 64 MB ram
        video (peak 33 MB/s write 66 MB/sec read) max 8MB vram, 8MB dram
        Control logic for pc-style peripheral devices
        8 slave DMA channels
        I/O cache controller (8 32 byte fully associative cache blocks)
        1-15 millisecond interval counter

Memory controller provides:
        1-8,16,32 byte writes
        1-8,16,32 byte reads
        8 byte video reads
        and 1-8 byte video write

DMA controller supports 8 seperate DMA controllers, each is able to
support a single read or write I/O data flow to and from the system memory and
the I/O device.  Each controller has a channel mode,channel enable, 
channel byte count, and channel address register.

A diagram shows the 8 devices as mouse and keyboard, parallel and serial ports,
prom, sound, NVRAM,floppy, rt clock, scsi, and ethernet

MCT-DP (PD31431) data path controller
Chip is basically a crossbar with 6 major connections:
        Vr4000 family data/adress to memory data lines (store)
        Memory data lines to the Vr4000 data/address (load)
        Vr4000 family data/address bus to the i386 data/address bus (I/O store)
        i386-style databus to the Vr4000 (I/O load)
        i386-style data bus to memory (DMA read)
        Memory data lines to the i386 data bus lines (DMA write)

Memory interlace is formed by the two MCT-DP chips is four words or 128 bits 
wide.  The chip contains a 128 bit write buffer that is used to buffer all 
data from the vr 4000 to the system.  The chip also contains 8 128 byte 
I/O data buffers which buffer data tranfers between the i386 style bus and 
the memory system.  These buffers allow concurrent vr4000 family memory 
operations and I/O direct memory access operations.

Not that I understand all of it but it sounds good to me.

Bill                                    1st>    Broadley@neurocog.lrdc.pitt.edu
Broadley@schneider3.lrdc.pitt.edu <2nd  3rd>                 Broadley+@pitt.edu
Linux is great.         Bike to live, live to bike.                      PGP-ok


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