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Re: My updated wishlist

To: riscy@pyramid.com
Subject: Re: My updated wishlist
From: caret@pyramid.com (Neil Russell)
Date: Tue, 6 Jul 93 21:49:56 PDT
In-reply-to: <9307070115.AA06457@unas.tss.no>; from "Tor Arntsen" at Jul 7, 93 3:15 am
Reply-to: riscy@pyramid.com
Sender: riscy-request@pyramid.com
> * Ethernet on board if feasible.  
>   BTW, my ISA 3c503/16 could achieve > 800KB/sec with net-1, less with net-2.
>   Donald Becker reported more than 900KB/sec with the WD8013.  Both the 3c503 
>   and the 8013 are NatSemi DP8390 based.
>   So ISA boards can give quite good performance, BUT also *sucks* CPU!
>   (runninng ttcp.)  Would it be efficient to have some DMA-based Ethernet? 
>   If so, I guess it should not be put into any ISA bus slot then, or what?
>   (If it's on board, and if it's only one interface type, I would prefer
>   BNC for thinnet.  If you want good arguments, see Donald Beckers' 
>   'Ethercard hardware tutorial' posted now and then at c.o.l :-)

It may be possible to get the IDT 3730 to do DMA to an ISA peripheral
even though the peripheral doesn't have DMA support.  Thus, we may be
able to get this type of performance without tying up the CPU any more
than it would be if the Ethernet were on the MB.

> * CPU: r3k is ok, the r4k2 would be even better of course.
>   I'm a bit worried about not having the possibility of adding an external
>   cache.  It's expensive to put in that fast static RAM of course, but it's
>   my impression that a good fast big cache could even outweigh using slower
>   DRAM (not that I'm suggesting using slow DRAM :-).
>   I must admit that I know next to nothing about the complexity level
>   of designing in an external cache, can anyone say something about chips,
>   cost, and design complexity level?

To get real performance, a CPUs cache must have close ties to the MMU.
On the R3000A, the cache controller is part of the CPU and presents
a 'tag' bus in addition to the regular address and data busses.  So
to attach cache to the R3000, you just add chips.  Unfortunately, you
also have to add a read buffer and some write buffers to assist the
pipeline.  On the 3051 series, all this is in the CPU chip.  To reduce
pin count (thus making a cheaper package), the tag bus is not available
outside the chip.  So we would have to implement a cache controller
outside.  The put this another way, it costs too much.

> * Timers.. I may have missed something, but don't we need some kind of 
>   timers to provide interrupts for the time slicing etc.  I would also like 
>   to play around with some high-definition timers (what about RT-Linux..).
>   Are there any built-in timers able to provide interrupts inside one of 
>   those smart I/O chips already mentioned?

Both the 3730 (peripheral controller) and the 3041 (I/O co-processor)
have a 24-bit timer which can be clocked quite fast.  So both peripheral
controller solutions that I proposed would cover that.

> * Keyboard controller on board, for IBM style keyboards (could it handle
>   PS/2 style keyboards?)

AT style keyboards will be supported.  If PS/2 ones are not compatible,
they will not work.  I can see no motivating reason why the should be.

Neil Russell            (The wizard from OZ)
Pyramid Technology                      Email:  caret@pyramid.com
3860 N. First Street                    Voice:  (408) 428-7302
San Jose, CA 95134-1702                   FAX:  (408) 428-8845


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