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My thoughts on the MB design...

To: drew@nagina.cs.Colorado.EDU
Subject: My thoughts on the MB design...
From: Jerry Callen <jcallen@Think.COM>
Date: Tue, 29 Jun 93 11:02:01 EDT
Cc: riscy@pyramid.com, jcallen@Think.COM
   Date: Tue, 29 Jun 1993 00:37:49 -0600
   From: Drew Eckhardt <drew@nagina.cs.Colorado.EDU>

   If we clock a 16 bit bus at 10Mhz, 0 wait states, we have 20M/sec 
   split between 5M/sec or 10M/sec SCSI and 1M/sec ethernet,
   more than enough. 

No, you DON'T have 20MB/sec, because there's a lot more to a bus
transaction than data transfer. If you can burst, you may get close to that
for brief periods, but doing word-at-time DMA you lose cycles to bus
arbitration/address cycles/other goo.

Sitting down with timing diagrams and working through bandwidth
calculations is a useful, if dull, exercise. It certainly gave me respect
for George's design of the pc532.

-- Jerry Callen
   jcallen@world.std.com           (preferred)
   jcallen@think.com               (OK, too)
   {uunet,harvard}!think!jcallen   (if you must)


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