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comments on today's batch o mail

To: riscy@pyramid.com
Subject: comments on today's batch o mail
From: adyer@zarniwoop (Andrew Dyer)
Date: Mon, 28 Jun 93 22:16 PDT
Several things bundled into one - here goes
Re: Frame buffers - some performance numbers for dedicated X-terminals

on a 1280x1024 8bpp display with VRAM and a 33 MHz IDT 3051 we got
approx. 45K Xstones (intermediate demo H/W)

on a 1280 x1024 8bpp display with VRAM, a 64bit bit-blitter unit and a
33MHz 3051 we got approx. 125K Xstones (Pagine C2000)

on a 1280x1024 mono display with VRAM and a 33MHz IDT 3051 we got 105K
Xstones. (Pagine M2000)

A HP i960 based 8 bp 1280x1024 terminal clocked in at about 90K Xstones.

Most 680x0 based systems (with or without 34010) seem to get
somewhere between 25 and 60K Xstones.

I would like to see the dumb frame buffer, because I think you could
do most of what a 34010 can do for less.  I think an FPGA with
download capability could be just the ticket.  Download a config file
for whatever video h/w you want, and away she goes!  This could handle
generating xfer addresses, syncs, shift clocks and all those nasty
'glue logic' functions for the video system.  Have video RAM use the
same controller as the DRAM and have the video controller do DMA to
reload the off half of the VRAM shift register.  Remember that a high
res frame buffer usually uses ECL oscillators and some ECL logic, so
don't forget those in the comparison. (You gotta get the 125MHZ
somewhere :-)

a 33Mhz 3051 with a single bank of 32 bit VRAM can access 16 bytes in
13 clocks, with interleaving the number goes down to 11 clocks.
(These are from memory so there is a possibility I am off by a clock)
This gives 40Mbyes/sec memory bandwidth (peak) for a non-interleaved
system, and a 48Mbyte/sec bandwidth (peak) for an interleaved system.

The main problems with the 34010 is the 16 bit host port and trying to
synchonize the X drawing code with the rest of the system. (Not to mention 
trying to split that code out of the base system).

re floppy and hard drive interfaces:

You should be able to find a combo chip that does all things, and just
put it on it's own little slow bus (or the ISA bus :-)) and use a fast
SCSI on a tighter coupled bus for real disk performance.

re other processors:

For true 32 bit CPUS market share says i960(KA/CA/CF). 29K is usually
listed second, next Sparc, and then MIPS.  (but noone else comes in
the 84 PLCC as far as I know)

One thought that occured to me (while I stopped to wash dishes) is
that one of the LSI logic MIPS derivatives might be interesting
because of the higher integration that they have - Especially the
LR33020 which is really meant to be a X-terminal on a chip (on chip
VRAM control, on-chip bit-blit, programmable chip selects, bus sizing)
About the only thing it doesn't have would be the FPU - and there is
probably a way to add that externally.  Comes in CPGA package cost was in
the low $100 range in volume a while ago.


Is there anything like a GPL for hardware?  We should stop to consider
how this thing we are talking about should be made available and under
what terms.

Final topic:
This thing needs a cool code-name.  How about a few suggestions?
Perhaps something recursive?


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