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Radical Video Idea

To: riscy@pyramid.com (Mips 3000)
Subject: Radical Video Idea
From: Bill Broadley <broadley@neurocog.lrdc.pitt.edu>
Date: Tue, 29 Jun 1993 07:43:29 -0500 (EDT)
I was trying to get a feel for how fast a mips 3081/51 + 3041 would be as a X11
machine.  What clock speed was the proposed 3041 as a video driver?  I'll call 
the 3041 cpu speed for the frame buffer X Mhz.

I looked around and found out that the decstation 3100 (16 Mhz mips 2000) has
a dumb frame buffer directly hooked up to the cpu.  If your interested in the 
setup/xserver check out "Writing Fast X Servers for Dumb Color Frame buffers."
A dec 3100 is a fairly fast xserver (for it's age anyways), I'd say better 
then an ET4000+linux anyways.  This should scale directly from 16.67 Mhz to
X Mhz.  I can run any benchmarks on the 3100 that people want.

In the "Smart Frame buffer" paper a 5200 (mips 3000 at 25 Mhz) with the frame 
buffer on the turbochannel is listed as having a max bandwidth of 30 MB/sec 
(writing big rectangles), or 15 MB/s for copying.   I'd expect more then this 
because it was on the turbo channel bus.  So our speed should scale as 
X Mhz/(25 Mhz * (1- % of turbochannel overhead)).

So the performance of a 3041 to drive the dumb frame buffer seems pretty good.  

Is it a reasonable thing to ask of a 3041 to generate a signal for horizontal
and vertical retrace?  For 1024x768 at 70 hz you need to generate 53,761 
retrace signals per second all that have to be accurate within a minimum of 1/
(1024*768*70) = 1/55,050,240 of a second.  Which gives you one pixel accuracy

Isn't that an easy thing to do directly?  I think using a second 3041 just
for an Xserver is a great idea.  Handling keyboard I/O, serial I/O seems
fairly direct.  Handling time critical video retraces sounds like it's 
not but then I'm in software..... 

This would make better use of the main's cpu ram, cache, cycles, context
swiches, memory bandwidth for running linux or applications.  The secondary 
processor would worry about I/O and running the Xserver.   I'd say of
all those things we are shortest on cache (most comprable machines have
128 k cache).

If this become impracticle maybe we should add a 256 k cache instead.

This way we get the advantages of an X11 specialized accelerator (directly
implements all of the Xprotocol) without the disadvantage of porting
X11 to a unsupported chipset.  You only need to learn one chip instead of 
two.  X11 should compile fine on a mips chip, as well as gcc.

Basically if the hardware guys can put it together it should be great.

Bill                                    1st>    Broadley@neurocog.lrdc.pitt.edu
Broadley@schneider3.lrdc.pitt.edu <2nd  3rd>                 Broadley+@pitt.edu
Linux is great.         Bike to live, live to bike.                      PGP-ok


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