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Re: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between

To: 徐成华 <>
Subject: Re: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between llsc
From: huangpei <>
Date: Sat, 12 Jan 2019 11:25:18 +0800
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hi, this is the patch for ll/sc bug in Loongson3 based on Linux-4.20

+. it cover all loongson3 CPU;

+. to fix the ll/sc bug *sufficiently and exactly*, this patch shows
how many places need to touch

+. it is built ok for on Loongson3 and Cavium/Octeon, old version is
tested in high pressure test

On Fri, 11 Jan 2019 20:40:49 +0800 (GMT+08:00)
徐成华 <> wrote:

> Hi Paul Burton,
> For Loongson 3A1000 and 3A3000, when a memory access instruction
> (load, store, or prefetch)'s executing occurs between the execution
> of LL and SC, the success or failure of SC is not predictable.
> Although programmer would not insert memory access instructions
> between LL and SC, the memory instructions before LL in
> program-order, may dynamically executed between the execution of
> LL/SC, so a memory fence(SYNC) is needed before LL/LLD to avoid this
> situation.
> Since 3A3000, we improved our hardware design to handle this case.
> But we later deduce a rarely circumstance that some speculatively
> executed memory instructions due to branch misprediction between
> LL/SC still fall into the above case, so a memory fence(SYNC) at
> branch-target(if its target is not between LL/SC) is needed for
> 3A1000 and 3A3000.
> Our processor is continually evolving and we aim to to remove all
> these workaround-SYNCs around LL/SC for new-come processor. 
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Attachment: 0001-loongson64-add-helper-for-ll-sc-bugfix-in-loongson3.patch
Description: Text Data

Attachment: 0002-loongson64-fix-ll-sc-bug-of-loongson3-in-inline-asm.patch
Description: Text Data

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