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Re: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between

To: Paul Burton <>
Subject: Re: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between llsc
From: Yunqiang Su <>
Date: Thu, 10 Jan 2019 01:59:07 +0000
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Thread-topic: [PATCH 1/2] MIPS: Loongson, add sync before target of branch between llsc

> 在 2019年1月10日,上午6:08,Paul Burton <> 写道:
> Hi YunQiang,
> On Sat, Jan 05, 2019 at 11:00:36PM +0800, YunQiang Su wrote:
>> Loongson 2G/2H/3A/3B is quite weak sync'ed. If there is a branch,
>> and the target is not in the scope of ll/sc or lld/scd, a sync is
>> needed at the postion of target.
> OK, so is this the same issue that the second patch in the series is
> working around or a different one?
> I'm pretty confused at this point about what the actual bugs are in
> these various Loongson CPUs. Could someone provide an actual errata
> writeup describing the bugs in detail?
> What does "in the scope of ll/sc" mean?

Loongson 3 series has some version, called, 1000, 2000, and 3000.

There are 2 bugs all about LL/SC. Let’s call them bug-1 and bug-2.

BUG-1:  a `sync’ is needed before LL or LLD instruction.
              This bug appears on 1000 only, and I am sure that it has been 
fixed in 3000.

BUG-2: if there is an branch instruction inside LL/SC, and the branch target is 
             of the scope of LL/SC, a `sync’ is needed at the branch target.
             Aka, the first insn of the target branch should be `sync’.
             Loongson said that, we don’t plan fix this problem in short time 
before they
             Designe a totally new core.

> What happens if a branch target is not "in the scope of ll/sc”?

At least they said that there won’t be a problem

> How does the sync help?
> Are jumps affected, or just branches?

I am not sure, so CC a Loongson people.
@Paul Hua

> Does this affect userland as well as the kernel?

There is few place can trigger these 2 bugs in kernel.
In user land we have to workaround in binutils:

In fact the kernel is the easiest since we can have a flavor build for Loongson.

> ...and probably more questions depending upon the answers to these ones.
>> Loongson doesn't plan to fix this problem in future, so we add the
>> sync here for any condition.
> So are you saying that future Loongson CPUs will all be buggy too, and
> someone there has said that they consider this to be OK..? I really
> really hope that is not true.

Bug is bug. It is not OK.
I blame these Loongson guys here.
Some Loongson guys is not so normal people.
Anyway they are a little more normal now, and anyway again, still abnormal.

> If hardware people say they're not going to fix their bugs then working
> around them is definitely not going to be a priority. It's one thing if
> a CPU designer says "oops, my bad, work around this & I'll fix it next
> time". It's quite another for them to say they're not interested in
> fixing their bugs at all.

They have interests, while I guess the true reason is that they have no enough
people and money to desgin a core, while this bug is quilt hard to fix.

> Thanks,
>    Paul

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