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Re: [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling

To: Hauke Mehrtens <>
Subject: Re: [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling
From: Paul Burton <>
Date: Mon, 7 Jan 2019 21:40:05 +0000
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Thread-topic: [PATCH 1/2] MIPS: lantiq: Fix IPI interrupt handling

Hauke Mehrtens wrote:
> This makes SMP on the vrx200 work again, by removing all the MIPS CPU
> interrupt specific code and making it fully use the generic MIPS CPU
> interrupt controller.
> The mti,cpu-interrupt-controller from irq-mips-cpu.c now handles the CPU
> interrupts and also the IPI interrupts which are used to communication
> between the CPUs in a SMP system. The generic interrupt code was
> already used before but the interrupt vectors were overwritten again
> when we called set_vi_handler() in the lantiq interrupt driver and we
> also provided our own plat_irq_dispatch() function which overwrote the
> weak generic implementation. Now the code uses the generic handler for
> the MIPS CPU interrupts including the IPI interrupts and registers a
> handler for the CPU interrupts which are handled by the lantiq ICU with
> irq_set_chained_handler() which was already called before.
> Calling the set_c0_status() function is also not needed any more because
> the generic MIPS CPU interrupt already activates the needed bits.
> Fixes 1eed40043579 ("MIPS: smp-mt: Use CPU interrupt controller IPI IRQ 
> domain support")
> Cc: # v4.12
> Signed-off-by: Hauke Mehrtens <>

Series applied to mips-fixes.


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