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Re: [PATCH v4 03/15] clk: ingenic: support PLLs with no bypass bit

To: Paul Cercueil <paul@crapouillou.net>
Subject: Re: [PATCH v4 03/15] clk: ingenic: support PLLs with no bypass bit
From: Stephen Boyd <sboyd@codeaurora.org>
Date: Thu, 28 Dec 2017 10:36:12 -0800
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Cc: Ralf Baechle <ralf@linux-mips.org>, Rob Herring <robh+dt@kernel.org>, Michael Turquette <mturquette@baylibre.com>, Mark Rutland <mark.rutland@arm.com>, Maarten ter Huurne <maarten@treewalker.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, linux-clk@vger.kernel.org
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References: <20170702163016.6714-2-paul@crapouillou.net> <20171228135634.30000-1-paul@crapouillou.net> <20171228135634.30000-4-paul@crapouillou.net>
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On 12/28, Paul Cercueil wrote:
> The second PLL of the JZ4770 does not have a bypass bit.
> This commit makes it possible to support it with the current common CGU
> code.
> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---

Acked-by: Stephen Boyd <sboyd@codeaurora.org>

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