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[PATCH 3.16 177/204] MIPS: AR7: Ensure that serial ports are properly se

To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: [PATCH 3.16 177/204] MIPS: AR7: Ensure that serial ports are properly set up
From: Ben Hutchings <ben@decadent.org.uk>
Date: Thu, 28 Dec 2017 17:05:44 +0000
Cc: akpm@linux-foundation.org, "Yoshihiro YUNOMAE" <yoshihiro.yunomae.ez@hitachi.com>, linux-mips@linux-mips.org, "Nicolas Schichan" <nschichan@freebox.fr>, linux-serial@vger.kernel.org, "Greg Kroah-Hartman" <gregkh@linuxfoundation.org>, "James Hogan" <jhogan@kernel.org>, "Jonas Gorski" <jonas.gorski@gmail.com>, "Florian Fainelli" <f.fainelli@gmail.com>, "Ralf Baechle" <ralf@linux-mips.org>, "Oswald Buddenhagen" <oswald.buddenhagen@gmx.de>
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3.16.52-rc1 review patch.  If anyone has any objections, please let me know.

------------------

From: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>

commit b084116f8587b222a2c5ef6dcd846f40f24b9420 upstream.

Without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is
never copied, resulting in a dead port.

Fixes: 154615d55459 ("MIPS: AR7: Use correct UART port type")
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
[jonas.gorski: add Fixes tag]
Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Yoshihiro YUNOMAE <yoshihiro.yunomae.ez@hitachi.com>
Cc: Nicolas Schichan <nschichan@freebox.fr>
Cc: Oswald Buddenhagen <oswald.buddenhagen@gmx.de>
Cc: linux-mips@linux-mips.org
Cc: linux-serial@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17543/
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
---
 arch/mips/ar7/platform.c | 1 +
 1 file changed, 1 insertion(+)

--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -581,6 +581,7 @@ static int __init ar7_register_uarts(voi
        uart_port.type          = PORT_AR7;
        uart_port.uartclk       = clk_get_rate(bus_clk) / 2;
        uart_port.iotype        = UPIO_MEM32;
+       uart_port.flags         = UPF_FIXED_TYPE;
        uart_port.regshift      = 2;
 
        uart_port.line          = 0;


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