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[PATCH 3.16 154/204] MIPS: Fix CM region target definitions

Subject: [PATCH 3.16 154/204] MIPS: Fix CM region target definitions
From: Ben Hutchings <>
Date: Thu, 28 Dec 2017 17:05:44 +0000
Cc:,, "Matt Redfearn" <>, "James Hogan" <>, "Ralf Baechle" <>, "Paul Burton" <>
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3.16.52-rc1 review patch.  If anyone has any objections, please let me know.


From: Paul Burton <>

commit 6a6cba1d945a7511cdfaf338526871195e420762 upstream.

The default CM target field in the GCR_BASE register is encoded with 0
meaning memory & 1 being reserved. However the definitions we use for
those bits effectively get these two values backwards - likely because
they were copied from the definitions for the CM regions where the
target is encoded differently. This results in use setting up GCR_BASE
with the reserved target value by default, rather than targeting memory
as intended. Although we currently seem to get away with this it's not a
great idea to rely upon.

Fix this by changing our macros to match the documentated target values.

The incorrect encoding became used as of commit 9f98f3dd0c51 ("MIPS: Add
generic CM probe & access code") in the Linux v3.15 cycle, and was
likely carried forwards from older but unused code introduced by
commit 39b8d5254246 ("[MIPS] Add support for MIPS CMP platform.") in the
v2.6.26 cycle.

Fixes: 9f98f3dd0c51 ("MIPS: Add generic CM probe & access code")
Signed-off-by: Paul Burton <>
Reported-by: Matt Redfearn <>
Reviewed-by: James Hogan <>
Cc: Matt Redfearn <>
Cc: Ralf Baechle <>
Signed-off-by: James Hogan <>
[bwh: Backported to 3.16: adjust context]
Signed-off-by: Ben Hutchings <>
 arch/mips/include/asm/mips-cm.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -173,8 +173,8 @@ BUILD_CM_Cx_R_(tcid_8_priority,     0x80)
 #define CM_GCR_BASE_GCRBASE_MSK                        (_ULCAST_(0x1ffff) << 
 #define CM_GCR_BASE_CMDEFTGT_SHF               0
 #define CM_GCR_BASE_CMDEFTGT_MSK               (_ULCAST_(0x3) << 0)
-#define  CM_GCR_BASE_CMDEFTGT_MEM              1
+#define  CM_GCR_BASE_CMDEFTGT_MEM              0
 #define  CM_GCR_BASE_CMDEFTGT_IOCU0            2
 #define  CM_GCR_BASE_CMDEFTGT_IOCU1            3

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