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Re: [P5600 && EVA memory caching question] PCI region

To: Yuri Frolov <>
Subject: Re: [P5600 && EVA memory caching question] PCI region
From: James Hogan <>
Date: Fri, 22 Dec 2017 11:49:39 +0000
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On Fri, Dec 22, 2017 at 02:18:26PM +0300, Yuri Frolov wrote:
> Sorry, I forgot to ask,
> > yes, the Malta implementation is slightly ugly as it relies on a
> > hardware physical memory alias of RAM starting at PA 0x80000000.
> any good docs about this hardware aliasing? I'm not sure I understand it 
> correctly, just want to understand things right.

Basically it keeps kseg0 (seg3) and kseg1 (seg2) pointing at PA 0, which
it runs kernel code from (i.e. same place it is loaded, without the EVA
layout enabled yet), but then it does data accesses from seg4 and seg5
which point at PA 0x80000000. I think the intention is to allow the VA
to PA offset to be the same for all cached segments.

However because the caches don't know that different physical addresses
refer to the same underlying RAM they aren't coherent with one another
and the kernel has to be careful not to use both, and to flush the
caches during boot.

Its not an approach I would personally recommend, and if we get EVA
support added to the generic platform I'd hope it would be a lot
cleaner, perhaps using the since added kernel self-relocation.


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