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Re: [P5600 && EVA memory caching question] PCI region

To: James Hogan <>
Subject: Re: [P5600 && EVA memory caching question] PCI region
From: Yuri Frolov <>
Date: Fri, 22 Dec 2017 12:37:14 +0300
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I'm looking at arch/mips/include/asm//mach-malta/kernel-entry-init.h and
there is a definition for SegCtl2:

          /* SegCtl2 */
          li      t0, ((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |      \
                  (6 << MIPS_SEGCFG_PA_SHIFT) |                           \
                  (1 << MIPS_SEGCFG_EU_SHIFT)) |                          \
                  (((MIPS_SEGCFG_MUSUK << MIPS_SEGCFG_AM_SHIFT) |         \
                  (4 << MIPS_SEGCFG_PA_SHIFT) |                           \
                  (1 << MIPS_SEGCFG_EU_SHIFT)) << 16)

it defines, that kernel logical addresses from the range 0x00000000 -
0x7fffffff are unmapped (no tlbs) and dictates, that in order to get a
physical address for any logical addresses from 0x00000000 - 0x3fffffff
range in kernel space, bits [31:29] of the logical address must be
changed to 100,
and (again in kernel space) for any logical addresses from 0x40000000 -
0x7fffffff range, bits [31:29] of the logical address must be changed to
110, right?
yes, the Malta implementation is slightly ugly as it relies on a
hardware physical memory alias of RAM starting at PA 0x80000000.

What physical addresses will logical addresses 0x00000000 and 0x20000000
be translated in kernel space?.. logical 0x00000000 --> physical
0x80000000, and logical 0x20000000 --> .... 0x80000000 too?
VA 0x20000000 -> PA 0xa0000000, since seg4 and seg5 are 1GB segments, so
its only bits 30 and up that can be changed.
Ah, I've got it now.
  I seem to remember the bit
corresponding to bit 29 isn't even writable in the SegCtl2 register.
I shoulda read the actual definition of SegCtl2, my bad. I presumed the definitions are the same for
SegCtl0 - SegCtl2.
Does that clarify things?
Yes, absolutely.  Thank you very much!

-- yuri

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