[Top] [All Lists]

[PATCH 01/14] MIPS: Fix CM region target definitions

Subject: [PATCH 01/14] MIPS: Fix CM region target definitions
Date: Tue, 19 Dec 2017 02:14:48 -0500
Cc: Paul Burton <>, Matt Redfearn <>, Ralf Baechle <>,, <>
List-archive: <>
List-help: <>
List-id: linux-mips <>
List-owner: <>
List-post: <>
List-software: Ecartis version 1.0.0
List-subscribe: <>
List-unsubscribe: <>
Original-recipient: rfc822;
From: Paul Burton <>

The default CM target field in the GCR_BASE register is encoded with 0
meaning memory & 1 being reserved. However the definitions we use for
those bits effectively get these two values backwards - likely because
they were copied from the definitions for the CM regions where the
target is encoded differently. This results in use setting up GCR_BASE
with the reserved target value by default, rather than targeting memory
as intended. Although we currently seem to get away with this it's not a
great idea to rely upon.

Fix this by changing our macros to match the documentated target values.

The incorrect encoding became used as of commit 9f98f3dd0c51 ("MIPS: Add
generic CM probe & access code") in the Linux v3.15 cycle, and was
likely carried forwards from older but unused code introduced by commit
39b8d5254246 ("[MIPS] Add support for MIPS CMP platform.") in the
v2.6.26 cycle.

Signed-off-by: Paul Burton <>
Reported-by: Matt Redfearn <>
Cc: Matt Redfearn <>
Cc: Ralf Baechle <>
Cc: <> # v3.15+
 arch/mips/include/asm/mips-cm.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index f6231b9..c6aaabd 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -142,8 +142,8 @@ static inline bool mips_cm_has_l2sync(void)
 GCR_ACCESSOR_RW(64, 0x008, base)
 #define CM_GCR_BASE_GCRBASE                    GENMASK_ULL(47, 15)
 #define CM_GCR_BASE_CMDEFTGT                   GENMASK(1, 0)
-#define  CM_GCR_BASE_CMDEFTGT_MEM              1
+#define  CM_GCR_BASE_CMDEFTGT_MEM              0
 #define  CM_GCR_BASE_CMDEFTGT_IOCU0            2
 #define  CM_GCR_BASE_CMDEFTGT_IOCU1            3

Intel Israel (74) Limited

This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.

<Prev in Thread] Current Thread [Next in Thread>
  • [PATCH 01/14] MIPS: Fix CM region target definitions, thirtsa . dreyfus <=