To: | James Hogan <james.hogan@mips.com> |
---|---|
Subject: | Re: [P5600 && EVA memory caching question] PCI region |
From: | Yuri Frolov <crashing.kernel@gmail.com> |
Date: | Fri, 15 Dec 2017 17:05:12 +0300 |
Cc: | linux-mips@linux-mips.org, paul.burton@mips.com |
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Hi, James On 12/14/2017 06:21 PM, James Hogan wrote: So, do I understand correctly, that provided we have these TLB entries in kernel,Hi Yuri, On Thu, Dec 14, 2017 at 06:03:11PM +0300, Yuri Frolov wrote:Hi, James. Do I understand correctly, that in case of CONFIG_EVA=y, any logical address from 0x00000000 - 0xBFFFFFFF (3G) range accessed from the kernel space is: 1) Unmapped (no TLB translations) 2) Is mapped 1:1 to physical addresses? E.g, readl from 0x20000000 is, in fact a read from physical address 0x20000000? I mean, in legacy memory mapping scheme, logical addresses 0x80000000 - 0xBFFFFFFF in kernel space were being translated to the physical addresses from the low 512Mb (phys 0x00000000 - 0x20000000), no such bits stripping or something for EVA, the mapping is 1:1?That depends on the EVA configuration. The hardware is fairly flexible (which is both useful and painful - making supporting EVA from multiplatform kernels particularly awkward), but that is one possible configuration. E.g. ideally you probably want to keep seg5 (0x00000000..0x3FFFFFFF) MUSK (TLB mapped for user & kernel) so that null dereferences from kernel code are safely caught, but that costs you 1GB of directly accessible physical address space from kernel mode. Index: 71 pgmask=16kb va=c0038000 asid=00[ri=0 xi=0 pa=200e0000 c=2 d=1 v=1 g=1] [ri=0 xi=0 pa=00000000 c=0 d=0 v=0 g=1] Index: 72 pgmask=16kb va=c0040000 asid=00[ri=0 xi=0 pa=200c0000 c=2 d=1 v=1 g=1] [ri=0 xi=0 pa=200c4000 c=2 d=1 v=1 g=1] u32 l; l = readl((const volatile void *)(0x200c0000 + 0x20)) and l = *(u32 *)(0xc0040000+ 0x20) should return the same value? As for userspace addresses, the addresses from the 0x00000000 - 0xBFFFFFFF range are: 1) Overlayed with the range which is directly accessible from the kernel spaceYes. Userland accesses access through tlb, kernel direct, and kernel eva accesses (LWE/SWE etc) access through tlb from kernel2) These addresses are mapped in userland, so, read from logical address 0x20000000 in userland may result in read from any physical address located in range 0x00000000 - 0xBFFFFFFF as defined by TLB for that particular userland thread?Yes, though it could in theory be any physical address mapped by the TLB, not just that range. Cheers James |
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