[RFC PATCH 04/16] MIPS: Add constant accessors for CP0.Context / CP0.XContext

[Matt Redfearn <matt.redfearn@mips.com>]

The current accessors are asm volatile meaning that the compiler cannot
optimise multiple requests for the value of these registers. Once
smp_processor_id() is switched to using these registers, this is
suboptimal. The Processor ID component of the register is constant, so
__read_const_32bit_c0_register / __read_const_64bit_c0_register can be
used to fetch the constant value and allow the compiler to optimise
multiple fetches. Barriers enforced by preempt_enable() ensure a re-read
of the register after preemption, when the running CPU may have changed.

Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
---

 arch/mips/include/asm/mipsregs.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 24d3028ba76d..67682acf8284 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1478,6 +1478,7 @@ do {                                                      
                \
 #define read_c0_globalnumber() __read_32bit_c0_register($3, 1)
 
 #define read_c0_context()      __read_ulong_c0_register($4, 0)
+#define read_const_c0_context()        __read_const_ulong_c0_register($4, 0)
 #define write_c0_context(val)  __write_ulong_c0_register($4, 0, val)
 
 #define read_c0_contextconfig()                __read_32bit_c0_register($4, 1)
@@ -1628,6 +1629,7 @@ do {                                                      
                \
 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
 
 #define read_c0_xcontext()     __read_ulong_c0_register($20, 0)
+#define read_const_c0_xcontext()       __read_const_ulong_c0_register($20, 0)
 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
 
 #define read_c0_intcontrol()   __read_32bit_c0_ctrl_register($20)
-- 
2.7.4