To: | David Daney <ddaney@caviumnetworks.com> |
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Subject: | Re: [PATCH v4 2/8] MIPS: Octeon: Enable LMTDMA/LMTST operations. |
From: | James Hogan <james.hogan@mips.com> |
Date: | Thu, 30 Nov 2017 23:12:01 +0000 |
Cc: | David Daney <david.daney@cavium.com>, <linux-mips@linux-mips.org>, <ralf@linux-mips.org>, <netdev@vger.kernel.org>, "David S. Miller" <davem@davemloft.net>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, <devel@driverdev.osuosl.org>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, <linux-kernel@vger.kernel.org>, "Steven J. Hill" <steven.hill@cavium.com>, <devicetree@vger.kernel.org>, Andrew Lunn <andrew@lunn.ch>, Florian Fainelli <f.fainelli@gmail.com>, Carlos Munoz <cmunoz@cavium.com> |
In-reply-to: | <c90ac3a5-7230-38ff-691a-3d94a25702cd@caviumnetworks.com> |
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References: | <20171129005540.28829-1-david.daney@cavium.com> <20171129005540.28829-3-david.daney@cavium.com> <20171130213635.GH27409@jhogan-linux.mipstec.com> <54c83e6b-35e2-be38-e4f1-87eb420938cb@caviumnetworks.com> <20171130225614.GJ27409@jhogan-linux.mipstec.com> <c90ac3a5-7230-38ff-691a-3d94a25702cd@caviumnetworks.com> |
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On Thu, Nov 30, 2017 at 03:09:33PM -0800, David Daney wrote: > On 11/30/2017 02:56 PM, James Hogan wrote: > > On Thu, Nov 30, 2017 at 01:49:43PM -0800, David Daney wrote: > >> On 11/30/2017 01:36 PM, James Hogan wrote: > >>> On Tue, Nov 28, 2017 at 04:55:34PM -0800, David Daney wrote: > >>>> Signed-off-by: Carlos Munoz <cmunoz@cavium.com> > >>>> Signed-off-by: Steven J. Hill <Steven.Hill@cavium.com> > >>>> Signed-off-by: David Daney <david.daney@cavium.com> > >>>> --- > >>>> arch/mips/cavium-octeon/setup.c | 6 ++++++ > >>>> arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++-- > >>>> 2 files changed, 16 insertions(+), 2 deletions(-) > >>>> > >>>> diff --git a/arch/mips/cavium-octeon/setup.c > >>>> b/arch/mips/cavium-octeon/setup.c > >>>> index a8034d0dcade..99e6a68bc652 100644 > >>>> --- a/arch/mips/cavium-octeon/setup.c > >>>> +++ b/arch/mips/cavium-octeon/setup.c > >>>> @@ -609,6 +609,12 @@ void octeon_user_io_init(void) > >>>> #else > >>>> cvmmemctl.s.cvmsegenak = 0; > >>>> #endif > >>>> + if (OCTEON_IS_OCTEON3()) { > >>>> + /* Enable LMTDMA */ > >>>> + cvmmemctl.s.lmtena = 1; > >>>> + /* Scratch line to use for LMT operation */ > >>>> + cvmmemctl.s.lmtline = 2; > >>> > >>> Out of curiosity, is there significance to the value 2 and associated > >>> virtual address 0xffffffffffff8100, or is it pretty arbitrary? > >> > >> Yes, there is significance. > >> > >> CPU local memory starts at 0xffffffffffff8000, each line is 0x80 bytes. > >> so the 2nd line starts at 0xffffffffffff8100 > > > > What I mean is, why is 2 chosen instead of any other value? > > That is explained in the change log of patch 5/8: > > > 1st 128-bytes: Use by IOBDMA > 2nd 128-bytes: Reserved by kernel for scratch/TLS emulation. > 3rd 128-bytes: OCTEON-III LMTLINE Ah yes. Perhaps it deserves a brief comment in the code, or even an enum. Cheers James
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