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Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1

To: Binbin Zhou <zhoubb@lemote.com>, Ralf Baechle <ralf@linux-mips.org>, James Hogan <james.hogan@imgtec.com>
Subject: Re: [PATCH v6 1/8] MIPS: Loongson: Merge PRID macro for Loongson-1A/1B/1C
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Thu, 30 Mar 2017 12:50:55 +0300
Cc: John Crispin <john@phrozen.org>, "Steven J . Hill" <Steven.Hill@imgtec.com>, Aurelien Jarno <aurelien@aurel32.net>, Fuxin Zhang <zhangfx@lemote.com>, Zhangjin Wu <wuzhangjin@gmail.com>, Kelvin Cheung <keguang.zhang@gmail.com>, Yang Ling <gnaygnil@gmail.com>, 谢致邦 <Yeking@Red54.com>, linux-mips@linux-mips.org, HuaCai Chen <chenhc@lemote.com>
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Hello!

On 3/30/2017 5:44 AM, Binbin Zhou wrote:

As we all know, the Loongson-1 series CPUs(1A/1B/1C) share the same PRID macro.
so I rename them for more readable.

   "Better readability", perhaps?

Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
Signed-off-by: HuaCai Chen <chenhc@lemote.com>
[...]

MBR, Sergei


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