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[PATCH V2 4/7] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

To: Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH V2 4/7] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
From: Huacai Chen <chenhc@lemote.com>
Date: Sat, 11 Mar 2017 13:19:55 +0800
Cc: John Crispin <john@phrozen.org>, "Steven J . Hill" <Steven.Hill@imgtec.com>, linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>, Zhangjin Wu <wuzhangjin@gmail.com>, Huacai Chen <chenhc@lemote.com>, stable@vger.kernel.org
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Some newer Loongson-3 has 64 bytes cache line size, so we select
MIPS_L1_CACHE_SHIFT_6.

Cc: stable@vger.kernel.org
Signed-off-by: Huacai Chen <chenhc@lemote.com>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e0bb576..c3c7d8a 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1373,6 +1373,7 @@ config CPU_LOONGSON3
        select WEAK_ORDERING
        select WEAK_REORDERING_BEYOND_LLSC
        select MIPS_PGD_C0_CONTEXT
+       select MIPS_L1_CACHE_SHIFT_6
        select GPIOLIB
        help
                The Loongson 3 processor implements the MIPS64R2 instruction
-- 
2.7.0


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