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Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA

To: "Maciej W. Rozycki" <macro@linux-mips.org>, Zenon Fortuna <zenon.fortuna@imgtec.com>
Subject: Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Date: Tue, 24 Feb 2015 13:06:22 -0800
Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>, "IMG - MIPS Linux Kernel developers" <IMG-MIPSLinuxKerneldevelopers@imgtec.com>, "Linux MIPS Mailing List" <linux-mips@linux-mips.org>
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On 02/23/2015 06:33 PM, Maciej W. Rozycki wrote:
On Mon, 23 Feb 2015, Zenon Fortuna wrote:

Does the current system-call "cacheflush(2)" works with the newer kernels?
As the "man cacheflush" tells, it was supposed to work only on MIPS based
systems.
  It absolutely has to work, on the MIPS target GCC emits code invoking it
to synchronise trampolines built at the run time on the stack (used for
calling nested functions, a C language extension borrowed from Pascal,
etc.), before passing execution there.  Verification of this syscall is
probably implicitly covered by the GCC test suite already.

   Maciej
cacheflush() syscall traps into kernel and it executes I and D caches flushing.

However, it's implementation in 'master' branch from Linus tree is wrong: if you call it in multicore environment for size > L1 cache size then it does it incorrectly: doesn't call IPI for index cacheops.

The correct way is ... sorry, can't find it in LMO...

- Leonid.


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