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Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA

To: "Maciej W. Rozycki" <macro@linux-mips.org>, Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Subject: Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.
From: "Steven J. Hill" <Steven.Hill@imgtec.com>
Date: Tue, 24 Feb 2015 10:20:59 -0600
Cc: Kevin Cernekee <cernekee@chromium.org>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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References: <1424362664-30303-1-git-send-email-Steven.Hill@imgtec.com> <1424362664-30303-2-git-send-email-Steven.Hill@imgtec.com> <CAJiQ=7DMBznB5Ths0sAZORf2hgSQRuBoPF-7HGHhcHn0EajnWg@mail.gmail.com> <54EBCC38.7000702@imgtec.com> <alpine.LFD.2.11.1502240217360.17311@eddie.linux-mips.org>
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On 02/23/2015 08:24 PM, Maciej W. Rozycki wrote:
> On Mon, 23 Feb 2015, Leonid Yegoshin wrote:
> 
>> The same is basically for transfer D$ --> I$ because in MIPS it is done via 
>> L2
>> or memory.
> 
>  The original issue aside (I don't want to dive into it) this I believe is 
> left to an implementer's discretion and there are MIPS implementations 
> indeed that fill I$ directly from D$; IIRC Alchemy silicon and its 
> descendants.
> 
>   Maciej
> 
I am tracking down even more HIGHMEM bugs, so I will rework these
patches, clean-up commit messages and post again. Thanks for all the
feedback.

Steve

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