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Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA

To: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Subject: Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.
From: "Maciej W. Rozycki" <macro@linux-mips.org>
Date: Tue, 24 Feb 2015 02:24:42 +0000 (GMT)
Cc: Kevin Cernekee <cernekee@chromium.org>, "Steven J. Hill" <Steven.Hill@imgtec.com>, IMG - MIPS Linux Kernel developers <IMG-MIPSLinuxKerneldevelopers@imgtec.com>, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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References: <1424362664-30303-1-git-send-email-Steven.Hill@imgtec.com> <1424362664-30303-2-git-send-email-Steven.Hill@imgtec.com> <CAJiQ=7DMBznB5Ths0sAZORf2hgSQRuBoPF-7HGHhcHn0EajnWg@mail.gmail.com> <54EBCC38.7000702@imgtec.com>
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On Mon, 23 Feb 2015, Leonid Yegoshin wrote:

> The same is basically for transfer D$ --> I$ because in MIPS it is done via L2
> or memory.

 The original issue aside (I don't want to dive into it) this I believe is 
left to an implementer's discretion and there are MIPS implementations 
indeed that fill I$ directly from D$; IIRC Alchemy silicon and its 
descendants.

  Maciej

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