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Re: [PATCH RFC v2 41/70] MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazar

To: David Daney <>
Subject: Re: [PATCH RFC v2 41/70] MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction
From: "Maciej W. Rozycki" <>
Date: Tue, 24 Feb 2015 00:33:29 +0000 (GMT)
Cc: Markos Chandras <>, Ralf Baechle <>,, Leonid Yegoshin <>
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On Mon, 23 Feb 2015, David Daney wrote:

> For the version of this patch currently in mips-for-linux-next: NACK
> There are two problems:
> 1) It breaks OCTEON, which will now crash in early boot with:
>   Kernel panic - not syncing: No TLB refill handler yet (CPU type: 80)
> 2) The logic is broken.
> The meaning of cpu_has_mips_r2_exec_hazard is that the EHB instruction is
> required.  You change the meaning to be that EHB is part of the ISA.

 Well, the macro is nowhere used I'm afraid, its last use was dropped with 
625c0a21, so it's rather difficult to assume any meaning to the macro.

 Also the intended meaning is clear from the commit message of 41f0e4d0, 
where the macro comes from, however unfortunately not from the definition 
of the macro itself.  It's a pity that along your change you did not 
include an explanatory note in arch/mips/include/asm/cpu-features.h.

 Finally, I think the change made to `build_tlb_write_entry' with 625c0a21 
may need to be reconsidered, as may perhaps the name itself of 
`cpu_has_mips_r2_exec_hazard' (why is it this place only that the macro 
was used? -- would it be better called `cpu_has_tlbw_exec_hazard' 
instead?), and then we'll need `cpu_has_ehb' or suchlike across all the 
other places.


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