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Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA

To: "Steven J. Hill" <Steven.Hill@imgtec.com>
Subject: Re: [PATCH V2 1/3] MIPS: Fix cache flushing for swap pages with non-DMA I/O.
From: Kevin Cernekee <cernekee@chromium.org>
Date: Fri, 20 Feb 2015 11:17:58 -0800
Cc: IMG-MIPSLinuxKerneldevelopers@imgtec.com, Linux MIPS Mailing List <linux-mips@linux-mips.org>
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On Thu, Feb 19, 2015 at 8:17 AM, Steven J. Hill <Steven.Hill@imgtec.com> wrote:
> From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
>
> Flush the D-cache before the page is given to a process
> as an executable (I-cache) page when the backing store
> is non-DMA I/O.
>
> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> Signed-off-by: Steven J. Hill <Steven.Hill@imgtec.com>

This patch seems to make several different changes to the cache
maintenance code all at once:

1) Add logic to handle virtually tagged D$ and perform extra flushes
on TLB updates

2) Add new write barriers betwen D$/I$ or D$/L2 flushes

3) Make __flush_anon_page() play nice with HIGHMEM on systems with cache aliases

and maybe a few more that I missed.

Would it be possible to split this out into individual commits, and
include more comprehensive changelogs for each one describing the
exact problem being solved?

Also, it would be helpful to clarify how this relates to the use of
swap (?) with a backing store that is non-DMA I/O.  Do you have an
example of a situation where the existing code broke?  A play-by-play
postmortem would make for interesting reading.

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